As shown schematically in FIG. 1, a memory device 1 of a known type, for example, of a non-volatile flash type, comprises a memory array 2 including a plurality of memory cells 3, which are arranged in rows and columns. Each row is coupled to a corresponding word line WL, whereas each column is coupled to a corresponding bit line BL.
Each memory cell 3 is formed by a storage element, which is formed by a floating-gate transistor. The gate terminal of the floating-gate transistor is coupled to a respective word line WL, whereas a first conduction terminal is coupled to a respective bit line BL; in addition, a second conduction terminal of the floating-gate transistor is connected to a reference potential (for example, a ground). The gate terminals of the memory cells 3 of a same row are thus connected to a same word line WL; moreover, the first conduction terminals of the memory cells 3 of a same column are connected to a same bit line BL.
A column-decoder circuit 4 and a row-decoder circuit 5 enable selection, on the basis of address signals received at input (designated as a whole by AS), of the memory cells 3, and in particular of the corresponding word lines WL and bit lines BL each time addressed, enabling biasing thereof at appropriate voltage and current values during the memory operations. In this connection, albeit not shown in detail in FIG. 1, both the column-decoder circuit 4 and the row-decoder circuit 5 are coupled to an address bus and are moreover provided with corresponding enable inputs, through which the circuits are notified of the fact that on the address bus a new address is present. The addresses and the signals for the enable inputs of the column-decoder circuit 4 and of the row-decoder circuit 5 are generated by a purposely provided circuitry (not shown).
The column-decoder circuit 4 provides a read path, which forms conductive paths between the bit line BL of the memory array 2 each time selected and a read-amplifier circuit 10. In turn, the read-amplifier circuit 10 is designed to compare the current circulating in each memory cell 3 addressed with a reference current in order to determine the corresponding data item stored.
As shown in FIG. 2, the read-amplifier circuit 10 comprises a biasing stage 11, designed to bias the bit lines BL of the memory array 2, and a current-to-voltage (I/V) converter stage 12, which are now described limitedly to the functions that they perform in regard to a bit line BL of the memory array 2, and thus limitedly to the portions that co-operate with the bit line BL of the memory array 2, on the hypothesis of the bit line BL having been addressed, i.e., selected.
The biasing stage 11 in turn comprises a biasing generator 13 and a pair of biasing transistors 14a, 14b, of an NMOS type in cascode configuration.
The biasing generator 13 receives at input a voltage that may be boosted (in what follows referred to as “boosted voltage Vboost”), for example by a charge-pump voltage-booster stage (not shown), and generates at output a biasing voltage Vcasc on a biasing node Np. Alternatively, and according to the value that it is desired to obtain for the biasing voltage Vcasc, the biasing generator 13 may receive directly a supply voltage Vdd, of a value lower than that of the boosted voltage Vboost.
The control terminals of the biasing transistors 14a, 14b are both connected to the aforesaid biasing node Np so as to receive the biasing voltage Vcasc.
Moreover, a first biasing transistor 14a of the pair has a first conduction terminal coupled to the bit line BL, from which it receives a cell-reading current Icell, through the read path formed by the column-decoder circuit 4; moreover, the first biasing transistor 14a comprises a second conduction terminal, which is connected to a first comparison input INa of the current-to-voltage converter stage 12.
The second biasing transistor 14b of the pair has a respective first conduction terminal coupled to a current-reference generator 15 (or, alternatively, to a reference cell, here not illustrated), from which it receives a reference reading current Iref, and a second conduction terminal, which is connected to a second comparison input INb of the current-to-voltage converter stage 12.
The current-to-voltage converter stage 12 moreover has a supply input, on which it receives the supply voltage Vdd, and is configured to make a comparison between the value of the cell-reading current Icell and the value of the reference reading current Iref, as well as for generating, on the basis of the result of this comparison, an output voltage Vout. The cell-reading current Icell traverses the memory cell 3 actually addressed, but not the other memory cells 3 coupled to the bit line BL, and is a function of the data item stored therein.
The read-amplifier circuit 10 further comprises a comparator stage 16, which receives at input the output voltage Vout from the current-to-voltage converter stage 12 and generates, on the basis of the value (for example, positive or negative) of this output voltage Vout, a digital reading signal Sout representing the data item stored in the memory cell 3 addressed.
In practice, the read-amplifier circuit 10 forms, for each bit line BL, a corresponding sense amplifier designed to generate, as a function of the corresponding cell-reading current Icell, the digital reading signal Sout.
FIG. 2 moreover shows a parasitic line capacitor 17, electrically coupled between the bit line BL and a ground reference, and a biasing capacitor 18, coupled between the biasing node Np and the ground reference itself.
This being said, the operation of reading of data items stored in the memory cells 3 envisages a first step of pre-charging of the corresponding bit lines BL. For example, in the case where, out of the bit lines BL, the bit line BL shown in FIG. 2 has been addressed, the biasing stage 11 and the first biasing transistor 14a carry out pre-charging of the bit line BL. More in particular, the first biasing transistor 14a enables application to the bit line BL shown in FIG. 2 of a desired pre-charging voltage, as a function of the biasing voltage Vcasc (in particular, this pre-charging operation enables charging of the parasitic capacitance 17).
The reading operation then envisages sensing of the cell-reading current Icell and its comparison with the reference reading current Iref in order to generate the output voltage Vout and, via the comparator stage 16, the digital output signal Sout. The cell-reading current Icell flows in the memory cell 3 coupled to the bit line BL shown in FIG. 2 and addressed, i.e., selected, via pre-charging, by the row-decoder circuit 5, of the corresponding word line WL. In this connection, from the standpoint of each word line WL, the behaviour of the row-decoder circuit 5 is comparable to that of a so-called inverter. Moreover, to select a word line WL, the row-decoder circuit 5 pre-charges (i.e., biases) the word line WL at a voltage such that the floating-gate transistor of a memory cell 3 coupled to the word line WL and to a bit line BL selected is in conduction. Instead, given a non-selected word line WL, the floating-gate transistors coupled thereto are inhibited.
As mentioned previously, the aforesaid cell-reading current Icell depends upon the data item stored in the memory cell 3 selected; consequently, the digital output signal Sout represents this stored data item.
For example, in the case where the cell-reading current Icell is greater than the reference reading current Iref, the digital output signal Sout may assume a high logic value (‘1’), whereas the digital output signal Sout may assume a low logic value (‘0’) in the case where the cell-reading current Icell is lower than the reference reading current Iref.
This being said, between presentation of a read command, i.e., (to a first approximation) generation of a new address and enabling of the column-decoder circuit 4 and of the row-decoder circuit 5, and generation of the corresponding digital output signals Sout (for example, on an output bus, not shown, and on the simplifying hypothesis that the delay introduced by the reading circuitry is zero) a period of time elapses known as “initial latency”. During the initial latency, the digital output signals Sout are not stable.
In greater detail, current memory devices are characterized by initial latencies that typically fall in the range between some tens of nanoseconds and some hundreds of microseconds. Values close to the lower limit of the aforementioned range are achieved by “embedded” memory devices, i.e., by memory devices integrated for example in microcontrollers. In these memory devices, it is possible to implement a high reading parallelism, thanks to the fact that it is not necessary to send the data items on an external bus of a predefined size (typically, sixteen bits). Instead, in the case of stand-alone memory devices, i.e., memory devices that may be interfaced with the outside world and are provided with a high number of columns (for example, tens of thousands of cells per row) the initial latency typically assumes values close to the upper limit of the aforementioned range.
In practice, today the initial latency represents one of the main causes that limit increase of dimensions of stand-alone memory devices. Moreover, in the case of embedded memory devices, the initial latency represents a lower limit for the so-called access time. For these reasons, irrespective of the type of memory device, there is felt the need to reduce the initial latency.